Modern designs need many interconnects for good performance. Cache coherent and non-coherent interconnects work together. It’s important for to have a good mix of both.
Accelerators and peripherals in don’t need cache coherency. But sharing memory and I/O is crucial so the processor has access to up-to-date data without leaving the chip. says its non-coherent interconnect IP and cache coherent IP work well together.
The latest version of its cache-coherent IP works with various processor IPs, including. has validated the for its cache coherent interconnect IP. The validation system boots Linux on a multi-cluster Arm design and tests critical cache coherency cases.
It supports many protocols, including , which is associated with the latest processors. Other protocols are , plus coherent interfaces. This allows designers to use older architectures and save money.
Interconnect IP is now certified by the certification agency . The version of interconnect design is certified, which means it is ready to use with I certification. The software side of has a user interface flow that starts with chip specifications and ends with generating .
maintains a database of inputs for SoC architectures, making managing specifications easier. says that modern electronics’ complexity presents challenges for SoC designers.
connect any processor using any protocol and topology. It supports different connectivity options for adaptable use in various applications across different markets like automotive, industrial, communications, and enterprise computing.
currently the primary supplier of memory chips for AI solutions. has received certification for accelerators, a significant breakthrough for the memory supplier. accelerators are expected to scale up later this year. Micron is catching up by launching for by the end of Q1 2024, with shipping starting in Q2 2024.
The rivalry between SK and is not just about being the first. Samsung uses non-conductive film technology for chips while SKuses mass reflow molded underfill method to address limitations.
SK has 60-70% yield rates for production, while only has 10-20%.
The process improves heat dissipation and production yields by injecting and hardening liquid material between silicon layers.
SK worked with and to adopt this technique and became the first to supply reportedly in contact with material suppliers but plans to stick to technology for upcoming chips.
Industry observers note that technology won’t be ready until 2025, so they may use both techniques.
